1. Field of the Invention
The present invention relates to a clock distribution circuit, and more specifically to a clock distribution circuit for use in a system-on-chip field in a gate array system (hereinafter referred to as an ASIC) obtained by combining a microprocessor macro including a CPU core and its peripheral circuit with a user circuit.
2. Description of the Prior Art
In an ASIC (application specific integrated circuits) obtained by combining a microprocessor macro including a CPU core and its peripheral circuit with a user circuit, it is well known that products designed by a cell-based system have been popularly marketed in a large volume project.
In the recent market, there is an increasing demand for a product in a microprocessor-macro-based platform design system formed by a CPU core and its peripheral circuit as a product in a small volume project. Especially, it is also well known that an easily designed product of a short TAT and a low cost by reuse of an IP (intellectual property) core is demanded.
As a product in the small volume project, An ASIC designed by a gate array system (a first prior art) obtained by combining a microprocessor macro including a CPU core and its peripheral circuit with a user circuit has also become popular in the market. An ASIC in the above mentioned first prior art is disclosed by, for example, Japanese Patent Laid-Open No. 2000-100952.
In the ASIC in the first prior art, a control circuit built in a CPU macrocell controls the timing or a sequence for smooth transmission/reception of a signal. Using the CPU macrocell having the above mentioned control circuit, a user of the ASIC of the first prior art can more easily control the CPU.
Furthermore, there is also a demand in the market for operating a microprocessor macro unit and a user circuit unit at different clock frequencies.
Therefore, in response to the request, an ASIC in a gate array system in a second prior art obtained by combining a microprocessor macro including a CPU core and its peripheral circuit with a user circuit is disclosed by, for example, Japanese Patent Laid-Open No. 7-295956 or Japanese Patent Laid-Open No. 11-272644.
Furthermore, an ASIC by a cell-based system with a similar configuration corresponding to the above mentioned demand is also well known.
A microprocessor including a CPU core unit and its peripheral circuit unit incorporated into the ASIC in the above mentioned second prior art has a configuration in which a user-specified clock frequency for operation of the microprocessor is distributed into the CPU core unit and the peripheral circuit unit.
Additionally, an ASIC of a cell-based system in a third prior art having a configuration in which a part (the CPU core unit or the peripheral circuit unit) of the clock frequency of the microprocessor macro unit formed by a CPU core and its peripheral circuit is distributed to the user circuit unit is also well known.
In a case where the user circuit unit could be requested to be operating at a clock frequency higher than the clock frequency of the microprocessor macro unit formed by a CPU core and its peripheral circuit, the user circuit unit includes a PLL (phase locked loop) circuit, and realizes a high-speed clock frequency.
However, since the ASIC in the above mentioned conventional gate array system has a user circuit unit in a gate array configuration, the chip size and the size of the user circuit unit are predetermined. In a case where a user requests to operate the user circuit unit at a clock frequency higher than the clock frequency of the microprocessor macro unit including a CPU core and its peripheral circuit by using the ASIC in the above mentioned conventional gate array system, there arises the problem that a user-requested circuit cannot be realized by a user circuit unit if the PLL (phase locked loop) circuit is incorporated into the user circuit unit configured by a gate array.
That is, when a PLL circuit is incorporated into a user circuit unit, a large number of the gates of the PLL circuit reduce the number of user circuit units available by the user, thereby disabling a user-requested user circuit to be realized by the user circuit unit.